The present invention relates to data processing, and more particularly to data transformations when data are transferred in networks.
It may be desirable to transform data when data are transferred in networks. For example, a router may replace physical addresses (MAC-layer addresses) in a data packet before transmission. An ATM switch may replace cell headers. Further, a router, a bridge, or some other device that transfers data between networks may perform protocol related transformations if the network on which the data are received and the network on which the data are transmitted use different protocols. See, for example, PCT publication WO 95/20282 (Jul. 27, 1995) incorporated herein by reference.
Such transformations can place a heavy burden on a network processor controlling the device. In addition, the processor may have to perform address resolution searches, screen out traffic that violates restrictions imposed for security reasons or in order to reduce congestion, and doing administrative work. Therefore, the processor performance is an important factor in achieving a high throughput in data transfers in networks.
To achieve high performance, some network processors are implemented as dedicated processors optimized for the specific tasks they have to perform in specific systems. These processors are sometimes hardwired for the specific tasks, protocols and standards. While these processors are fast, they have a disadvantage that they are not easily adaptable to a wide range of tasks, protocols, and standards. Therefore, such processors have limited applicability.
There also exist more intelligent processors adaptable to a wide range of systems having different tasks, protocols and standards. Examples are software programmable processors. However, the higher intelligence often comes at the cost of performance. In particular, software programmable processors can be considerably slower than their hardwired counterparts.
To combine high throughput with adaptability some devices use multiple software programmable processors. However, multiple software programmable processors can make the device expensive.
There is therefore a need for an inexpensive, adaptable, high-throughput processor arrangement.